The present invention relates to a data processing device and electronic equipment.
In pipeline architecture, if a branch instruction or a loop instruction occurs, a branch target instruction must be newly fetched for execution. Therefore, in pipeline architecture consisting of “Fetch”, “Decode”, “Execution”, and “Write”, three clock cycles are wasted each time a branch (including a branch in a loop) occurs.
There may be a case where a branch prediction circuit is provided for a microcomputer in order to prevent such a waste of clock cycles. However, since tens of thousands of gates are necessary for realizing the branch prediction circuit, adding the branch prediction circuit inevitably increases the circuit scale and cost.